CMOS PLL Synthesizers - Analysis and Design by K. Shu, E. Sinencio

By K. Shu, E. Sinencio

Because of the development of semiconductor and conversation know-how, the instant verbal exchange industry has been booming within the final twenty years. It developed from uncomplicated pagers to rising third-generation (3G) mobile telephones. in the intervening time, broadband conversation marketplace has additionally won a quick development. because the industry constantly calls for hello- functionality and reasonably cheap items, circuit designers are looking for hello- integration communique units in reasonable CMOS know-how. The phase-locked loop frequency synthesizer is a serious part in verbal exchange units. it really works as an area oscillator for frequency translation and channel choice in instant transceivers and broadband cable tuners. It additionally performs a huge position because the clock synthesizer for information converters within the analog-and-digital sign interface. This ebook covers the layout and research of PLL synthesizers. It comprises either basics and a evaluate of the state of the art options. The temporary research of the third-order charge-pump PLL unearths its locking habit adequately. The behavioral-level simulation of PLL additional clarifies its balance restrict. layout examples are given to obviously illustrate the layout technique of PLL synthesizers. an entire derivation of reference spurs within the charge-pump PLL can also be awarded during this e-book. The in-depth research of the electronic CA modulator for fractional-N synthesizers presents insightful layout instructions for this crucial block

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Wolaver, Phase-locked Loop Circuit Design. New Jersey: Prentice Hall, 1991 [51] D. D. dissertation, Columbia University, New York, May 2000 [52] H. Liu and A. Karsilayan, “An automatic tuning scheme for high-frequency bandpass filters,” in Proc. IEEE ISCAS, vol. 3, Phoenix, AZ, May 2002, pp. 551-554 [53] J. Savoj and B. Razavi, High-speed CMOS Circuits for Optical Receivers. Boston, MA: Kluwer, 2001 [54] B. Razavi, Monolithic Phase-locked Loops and Clock Recovery Circuits. New York: IEEE Press, 1996 This page intentionally left blank Chapter 3 PLL FREQUENCY SYNTHESIZER This chapter presents the analysis of PLL-based frequency synthesizers.

The block diagram of a DLL-FS is shown in Fig. 2-12. 2. FREQUENCY SYNTHESIZER FOR WIRELESS APPLICATIONS 21 Figure 2-12. 5 Hybrid frequency synthesizer Many systems incorporate a mixture or hybrid of these basic approaches in order to take advantage of the benefits of increased speed or improved resolution that one approach may have over another. For example, sometimes a PLL synthesizer may incorporate a DDS in its reference circuitry to increase resolution or to reduce switching time [47]. A major drawback of this approach is that the PLL acts as a multiplier on any phase noise or spurs in its reference and a DDS may have high spurs.

Weigandt, and P. Gray, “PLL/DLL system noise analysis for low jitter clock synthesizer design,” in Proc. IEEE Int. Symp. Circuits and Systems (ISCAS), vol. 4, London, UK, May 1994, pp. 31-34 A. Demir, A. Mehrotra, and J. Roychowdhury, “Phase noise in oscillators: a unifying theory and numerical methods for characterization,” IEEE Trans. Circuits Syst. I, vol. 47, pp. 655-674, May 2000 L. D. dissertation, The University of Minnesota, Ann Arbor, MI, 2002 C. Samori, A. Lacaita, A. Zanchi, and F. Pizzolato, “Experimental verification of the link between timing jitter and phase noise,” Electronic Letters, vol.

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